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Difference between revisions of "User:Green Sprite"
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=Dwarftel Core d1= | =Dwarftel Core d1= | ||
==Memory Cell== | ==Memory Cell== | ||
| + | ===Single bit cell=== | ||
Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br> | Design for single bit memory cell found [[Memory_(computing)#Minecart_Logic|here]]<br> | ||
| + | ===Byte cell=== | ||
Design for byte: | Design for byte: | ||
<diagram fg=7:0> | <diagram fg=7:0> | ||
| Line 12: | Line 14: | ||
</diagram> | </diagram> | ||
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design. | The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design. | ||
| + | ===Memory write=== | ||
| + | Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in the registry connects to the {{Raw Tile|☼|#0F0}} northern gear assembly, and also to the {{Raw Tile|☼|#080}} sourthern gear assembly. The northern gear assembly is inverted. | ||
Revision as of 01:38, 5 June 2021
Dwarftel Core d1
Memory Cell
Single bit cell
Design for single bit memory cell found here
Byte cell
Design for byte:
| O | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╗ |
| ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ |
| ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ |
| ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O |
| ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ |
| ╚ | ╩ | ═ | ═ | ╩ | ╩ | ═ | ═ | ╩ | ╩ | ═ | ═ | ╩ | ╩ | ═ | O |
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.
Memory write
Multiple byte cells are created close together to create the actual memory. A registry for writing to memory, consisting of a byte cell is created. The pressure plate in the registry connects to the ☼ northern gear assembly, and also to the ☼ sourthern gear assembly. The northern gear assembly is inverted.