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Difference between revisions of "User:Green Sprite"
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[%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O | [%200][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205][%205][%202][%202][%205]O | ||
</diagram> | </diagram> | ||
| + | The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design. | ||
Revision as of 00:46, 5 June 2021
Dwarftel Core d1
Memory Cell
Design for single bit memory cell found here
Design for byte:
| O | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╦ | ═ | ═ | ╦ | ╗ |
| ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ | ╥ | ☼ | ╚ | ╝ |
| ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ | ║ | O | ╥ | ☼ |
| ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O | ╨ | ☼ | ║ | O |
| ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ | ╔ | ╗ | ╨ | ☼ |
| ╚ | ╩ | ═ | ═ | ╩ | ╩ | ═ | ═ | ╩ | ╩ | ═ | ═ | ╩ | ╩ | ═ | O |
The byte cell is made up of eight individual single bit memory cells. The diagram shows only the track layer, the minecart and roller/furniture layers can be derived from the diagram above and the single bit design.